1. Technical Field
The present invention relates in general to clock signal distribution within an integrated circuit and in particular, to a high speed buffer for enhancing clock signal distribution. Still more particularly, the present invention relates to a high speed resonant buffer for providing high speed clock signal distribution within an integrated circuit.
2. Description of the Related Art
Synchronization of logic circuits within an integrated circuit is accomplished by distributing a master clock signal to timing critical sub-circuits. The proper operation of an information processing unit, such as a microprocessor, requires that digital data is in the proper state when data is transferred by the clock signal. In all "clocked" systems there is a master clock which synchronizes circuits and controls the transfer of data.
Typically, an oscillator within an integrated circuit produces a clock signal and a central buffer amplifies the signal for distribution to digital sub-circuits. Interconnection of sub-circuits which are not adjacent on an integrated circuit substrate requires relatively long conductors to be fabricated on the integrated circuit. Integrated circuits are becoming larger and the distance separating sub-circuits is increasing. When the distance from a driving transistor within a central buffer to a receiving transistor of a sub-circuit becomes long enough to adversely effect a signal's characteristics and propagation time, the interconnecting wire can be referred to as a "long wire".
The resistance (R) of a wire increases linearly as a function of wire length (l) and, the resistance per unit length (r) of the material utilized, where R=rl. Likewise, the capacitance of a wire (C) increases linearly with its length (l) and capacitance per unit length (c). Capacitance can be defined by C=cl. The "R-C" delay (D) of a wire due to resistance and capacitances is D=(1/2)rcl.sup.2.
As depicted above by the l.sup.2 term, the delay due to the capacitive and resistive effects increases quadratically with the length of a wire. As clock speeds and the scale of integrated circuits continues to increase, timing difficulties associated with wire lengths have become a vexing problem.
Consumer demand for faster processing and higher clock frequencies has intensified the effort to find a solution for synchronization problems associated with clock signal distribution in the frequency range of one gigahertz.
The R-C delay associated with circuit interconnection is prone to process variations across the chip because the product (R-C) depends on the thickness of the conductor and the fabrication of the dielectric layers. Process variations result in intolerable timing skews in separate geographical areas of the integrated circuit. Unacceptable delay, bandwidth, and process tolerance due to R-C networks have forced circuit designers to create improved transmission line clock distribution circuits for digital circuits operating at gigahertz frequencies. The propagation delay in transmission lines is dependent only on the velocity of light in the dielectric medium surrounding the interconnects, delay is thus independent of the geometry of the interconnects and immune to variations resulting from fabrication processes. Transmission line circuits also exploit the inductive overshoot effects which result in sharp clock rise times that are critical for achieving fast response in digital latches and registers.
Transmission line distribution circuits originating from a central buffer form a "tree structure." A tree structure distributes clock signals to "load buffers" via "intermediate buffers". Intermediate buffers are optional and are deployed to maintain signal integrity. In typical microprocessor designs, each load buffer drives a capacitive load of about 1 nF. The 1 nF capacitance represents the input capacitance of load subcircuits, latches, and registers. The characteristic impedance of transmission lines is of the order of 50 ohms.
In order to attain clock signal rise times of less than 100 picoseconds (i.e. 10% of the clock period), the input capacitance of the load buffers has to be less than 2 picofarads. In conventional designs, buffers are cascaded to comprise a chain of inverters. Typically, a driving inverter supplies a receiving inverter and the receiving inverter is about three times larger in size than the driving inverter.
The scaling factor of three (i.e., =2.718 to be exact) results in optimal delay and acceptable clock signal rise times. Typically, the number of stages of load buffers in a clock distribution system is on the order of Log.sub.e (C.sub.load /C.sub.input) or 6 buffers. The large number of inverts utilized as load buffers causes timing skews due to across chip channel length variations, increased chip area, and constraints in chip layout and planning. The output resistance of the last inverter stage in the load buffer must necessarily be less than 0.1 ohms in order to attain clock signal rise times of less than 100 ps for 1 nF load capacitances. Such low impedances result in large current transients (.about.10 A) during clock signal transitions, and high instantaneous currents create many problems in the power distribution network.
It should therefore be apparent that it would be advantageous to provide an integrated circuit clock distribution system which distributes an acceptable clock signal at very high clock speeds and requires a minimal quantity of buffers. Additionally, it would be advantageous to provide a clock distribution system which functions effectively with small buffers.